1. Field of the Invention
The present invention relates to electronic devices, and in particular, to reworkable C4 encapsulated integrated circuit chips and their method of manufacture.
2. Description of Related Art
Electronic components utilizing integrated circuit chips are used in a number of applications. Controlled Collapse Chip Connection is an interconnect technology developed by IBM as an alternative to wire bonding. This technology is generally known as C4 technology or flip chip packaging. Broadly stated, one or more integrated circuit chips are mounted above a single or multiple layer substrate and pads on the chip are electrically connected to corresponding pads on the substrate by a plurality of electrical connections such as solder bumps. The integrated circuit chips may be assembled in an array such as a 10.times.10 array. The substrate is then electrically connected to another electronic device such a circuit board with the total package being used in an electronic device such as a computer. An array of integrated circuit chips and an apparatus for cooling the integrated circuit chips is shown in U.S. Pat. No. 5,239,200 which patent is hereby incorporated by reference.
Flip chip packaging is described in U.S. Pat. No. 5,191,404 which patent is hereby incorporated by reference. In general, flip chip joining is desirable for many applications because the footprint or area required to bond the chip to the substrate is equal to the area of the chip itself. Flip chip joining also exploits the use of a relatively small solder bump which typically measures a height of approximately 1 mil to 1.5 mils and a width of approximately 2 to 4 mils to join the pad on the chip to a corresponding pad on the substrate. Electrical and mechanical interconnects are formed simultaneously by reflowing the bumps at an elevated temperature. The C4 joining process is self-aligning in that the wetting action of the solder will align the chip's bump pattern to the corresponding substrate pads. This action compensates for chip to substrate misalignment up to several mils incurred during chip placement. In "Microelectronics Packaging Handbook" edited by R. R. Tummala and E. J. Rymaszewski, 1989, Van Nostrand Reinhold, pages 361-391, C4 chip to package interconnections are discussed and this reference is hereby incorporated by reference.
In the finished flip chip package there is an opening or space between the pad containing surface of the integrated circuit chip and the pad containing surface of the substrate resulting from the thickness of the solder bump connection between the pads. This open space can not be tolerated because any interference with the solder connections will adversely affect the performance of the package. For example, moisture, the infusion of thermal paste used to increase heat transfer from the chip and the mechanical integrity of the chip possibly breaking the electrical connections are all serious problems. To solve this problem integrated circuit chips are encapsulated in a suitable plastic package to protect the integrated circuit chip mechanically, electrically and chemically. In the C4 technology the chip opening is encapsulated totally or in many cases a sealant is used around the chip edges to seal the opening. Presently, non-reworkable sealants which are thermoset highly cross linked materials are used. These materials are insoluble and do not liquefy on heating and are generally applied in a low viscosity, unpolymerized form without any solvent and are polymerized in place. Epoxies are generally used and while useful for many applications generally restrict the use of C4 joining to single chip modules because they cannot be easily reworked and the complete module is replaced when it malfunctions. Other encapsulation materials have been developed but these are expensive and require expensive solvents to remove the encapsulant from the substrate.
The encapsulation of integrated circuit chips to improve their reliability is well known and a number of patents have issued in this area. Most of the patents, however, show the use of chips wire bonded or tap bonded and the chip is completely encapsulated in a transfer molded thermoset or thermoplastic polymer. Basically, this process involves melting the polymer in a cavity within the mold. A plunger then rams the molten polymer through an orifice into the mold ventricle. The integrated circuit chip and substrate are bonded to each other using a polymeric adhesive and the package is placed in the mold and the molten polymer forces in and around the package to totally encapsulate the device. A number of patents have issued in this area including: U.S. Pat. Nos. 4,632,798; 4,736,012; 4,750,092; 4,758,875; 4,952,122; 5,040,047; 5,057,903; 5,191,404; 5,225,499; 5,300,808; 5,309,321; and 5,344,795. The disclosures of the above patents are hereby incorporated by reference. Flip chip bonding offers many advantages in electronics manufacture compared to the complete encapsulation techniques above. One of the most important being the ability to remove and replace the chip without scrapping the chip or substrate. This removal and replacement termed rework can be performed numerous times without degrading quality or reliability.
Encapsulation of the flip chip packages however presents many problems. The flip chip package must be reliable and thermal mismatches between the encapsulant and the chip, substrate or solder bumps must be minimized to avoid stressing and damaging of the package. The encapsulant must be able to withstand the solder joining process temperatures. And further, the C4 encapsulated chip should also be reworkable to facilitate its usefulness.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide an integrated circuit chip containing electronic package wherein pads on the chip are electrically connected to pads on a substrate by solder connections wherein the solder area is effectively sealed (encapsulated) to provide mechanical, electrical and chemical reliability and which chip is capable of being reworked in the event of a malfunction of the package.
It is another object of the present invention to provide a method for making a reworkable integrated circuit chip containing package having enhanced electrical, mechanical and chemical reliability properties wherein pads on the chip are electrically connected to pads on an interconnection substrate by electronic solder connections.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.